Authors
Citation
J. Monteiro et S. Devadas, TECHNIQUES FOR POWER ESTIMATION AND OPTIMIZATION AT THE LOGIC LEVEL -A SURVEY, Journal of VLSI signal processing systems for signal, image, and video technology, 13(2-3), 1996, pp. 259-276
Citations number
63
Categorie Soggetti
Computer Sciences, Special Topics","Engineering, Eletrical & Electronic","Computer Science Information Systems
Journal title
ISSN journal
13875485
Volume
13
Issue
2-3
Year of publication
1996
Pages
259 - 276
Database
ISI
SICI code
1387-5485(1996)13:2-3<259:TFPEAO>2.0.ZU;2-5
Abstract
We present a survey of state-of-the-art power estimation methods and o
ptimization techniques targeting low power VLSI circuits. Estimation a
nd optimizations at the circuit and logic levels are considered.