This paper proposes a pilot project to study the feasibility of a nume
rical accelerator installation at CERN with a long term target (LHC st
artup time frame) of real-time performance. The rapid evolution of mic
roprocessors based on RISC architectures, the ever increasing system i
ntegration level and the associated compiler technology now provides t
he opportunity to imagine a numerical accelerator. In the next few yea
rs, the increased speed of microprocessors and the computer systems as
a whole, as indicated by technology road maps from various manufactur
ers should enable the real time simulation of large machines such as t
he LHC.