A MODIFIED ART-1 ALGORITHM MORE SUITABLE FOR VLSI IMPLEMENTATIONS

This paper presents a modification to the original ART 1 algorithm (Ca rpenter & Grossberg, 1987a, A massively parallel architecture for a se lf-organizing neural pattern recognition machine, Computer Vision, Gra phics, and Image Processing, 37, 54-115) that is conceptually similar, can be implemented in hardware with less sophisticated building block s, and maintains the computational capabilities of the originally prop osed algorithm. This modified ART 1 algorithm (which we will call here ART 1(m)) is the result of hardware motivated simplifications investi gated during the design of an actual ART 1 chip [Serrano-Gotarredona e t al., 1994, Proc. 1994 IEEE Int. Conf. Neural Networks (Vol. 3, pp. 1 912-1916); Serrano-Gotarredona & Linares-Barranco, 1996, IEEE Trans. V LSI Systems, (in press)]. The purpose of this paper is simply to justi fy theoretically that the modified algorithm preserves the computation al properties of the original one and to study the difference in behav ior between the two approaches. Copyright (C) 1996 Elsevier Science Lt d.