IMPROVING CACHE PERFORMANCE WITH BALANCED TAG AND DATA PATHS

There are two concurrent paths in a typical cache access - one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path thro ugh the tag array determines cache hit/miss and, for set-associative c aches, selects the appropriate line from within the selected set. In b oth direct-mapped and set-associative caches, the path through the tag array is significantly longer than that through the data array. In th is paper, we propose a path balancing technique to help match the dela ys of the tag and data paths. The basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-on e relationship between address tags and cache lines so as to achieve a design that provides higher performance. Performance evaluation using both TPC-C and SPEC92 benchmarks shows that this path balancing techn ique offers impressive improvements in overall system performance over conventional cache designs. For TPC-C, improvements in the range of 6 % to 28% are possible.