A HIGH-PERFORMANCE 0.35-MU-M 3.3-V BICMOS TECHNOLOGY OPTIMIZED FOR PRODUCT PORTING FROM A 0.6-MU-M 3.3-V BICMOS TECHNOLOGY

A 0.35-mu m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect [1], A 2. 5-V version offers lower power and higher performance, A 3.3-V BiCMOS version has been optimized for compatibility with previous designs imp lemented in a 0.6-mu m 3.3-V BiCMOS process, A two-step design process for converting an existing production worthy 0.6-mu m 3.3-V BICMOS de sign to a 0.35-mu m design is described, The silicon results are descr ibed.