A 2.4 GB S RECEIVER AND A 1/16 DEMULTIPLEXER IN ONE-CHIP USING A SUPER SELF-ALIGNED SELECTIVELY GROWN SIGE BASE (SSSB) BIPOLAR-TRANSISTOR/

This paper reports a 2.4 Gb/s optical terminal IC that integrates high -speed analog and digital circuits for future optical networks using 6 0-GHz f(T) self-aligned silicon-germanium (SiGe)-alloy base bipolar tr ansistors, The selective epitaxial growth (SEG) SiGe base was formed b y using cold-wall ultra-high vacuum (UHV)/CVD technology. Boron concen tration reduction at the SiGe epitaxial layer/Si-substrate interface b y using a new treatment prior to SEG leads to electrical characteristi cs with less dependence on bias voltage, The IC consists of a receiver (a preamplifier, an automatic gain control (AGC) amplifier, a phase-l ocked loop (PLL), and a D-type flip-flop (D-F/F)), and a 1:16 demultip lexer (DMUX), An input offset control circuit is included in the AGC a mplifier for wide dynamic range, Trench isolation and silicon-on-insul ator (SOI) technologies are introduced to reduce crosstalk between the amplifiers and the PLL, Power consumptions are 0.6 W at -5.2 V for th e analog part and 0.45 W at -3.3 V for the digital part, which does no t include the ECL output buffers.