This paper presents a monolithic comparator implemented in a 0.5-mu m
SiGe heterojunction bipolar transistor (HBT) process, The SiGe HBT pro
cess provides HBT npn transistors with maximum f(T) over 40 GHz and f(
max) over 55 GHz, The comparator circuit employs a resettable slave st
age, which was designed to produce return-to-zero output data, Operati
on with sampling rates up to 5 GHz has been demonstrated by both simul
ation and experiments, The comparator chip attains an input range of 1
.5 V, dissipates 89 mW from a 3-V supply, and occupies a die area of 4
07 x 143 mu m(2). The comparator is intended for analog-to-digital (A/
D) conversion of 900 MHz RF signals.