SYSTEM-LEVEL DESIGN FOR TEST OF FULLY DIFFERENTIAL ANALOG CIRCUITS

Several designs for test techniques for fully differential circuits ha ve recently been proposed. These techniques are based on the inherent data encoding, the fully differential analog code (FDAC), present in d ifferential circuits, These techniques have not previously been verifi ed experimentally. In this paper, we report results from a fabricated test chip which incorporates design for test structures, The test chip is a fully differential fifth-order filter, and was fabricated on a 2 -mu m CMOS process, The test techniques implemented are derived from a system-level technique developed earlier. The test chip contains faul t injection circuitry to emulate faults, Our results demonstrate that the FDAC is a viable design for test technique for analog circuits.