CIRCUIT TECHNIQUES FOR CMOS LOW-POWER HIGH-PERFORMANCE MULTIPLIERS

In this paper we present circuit techniques for CMOS low-power high-pe rformance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-mu m CMOS (in BiCMOS) technology, The complem entary pass-transistor logic-transmission gate (CPL-TG) full adder imp lementation provided an energy savings of 50% compared to the conventi onal CMOS full adder, CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMO S implementation, Although the circuits were optimized for (16 x 16)-b multiplier using the Booth algorithm, a (6 x 6)-b implementation was used as a test vehicle in order to reduce simulation time, For the (6 x 6)-b case, implementation based on CPL-TG resulted in 18% power savi ngs and 30% speed improvement over conventional CMOS.