A PARALLEL-PROCESSING CHIP WITH EMBEDDED DRAM MACROS

A combined DRAM and logic chip has been developed for massively parall el processing (MPP) applications, A trench cell 4-Mb CMOS DRAM technol ogy is used to fabricate the chip with an additional third-level metal layer, The 5-V 0.8-mu m technology merges 100-K gate custom logic cir cuits and 4.5-Mb DRAM onto a 14.7 x 14.7 mm(2) die. The DRAM design is based on a 32-K x 9-b (288-Kb) self-consistent macro form, It has ind ependent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements, The logic part of the chip consists of eight 16-b CPU's and some broadcast logic circuits, Each CPU and two D RAM macros (64-KB) comprise a processing element (PE), and hypercube c onnections among eight PE's are made for the scalable MPP capability, Each chip delivers 50-MIPS of performance at 2.7 W.