Rv. Jaworski et R. Harjani, ANALOG IMPLEMENTATION OF THE FDTS DF DETECTION ALGORITHM FOR MAGNETICRECORDING/, IEEE transactions on magnetics, 32(5), 1996, pp. 3944-3946
An analog implementation of the fixed delay tree search algorithm for
magnetic recording detection is presented. The circuit is designed usi
ng a 1.2um BiCMOS process with NPN devices with an f(t) of 12GHz, and
provides a reference for the feasibility of an analog implementation.
Composite simulation results of all the system blocks suggest operatin
g speeds in excess of 100MSamples/s with a total power consumption of
less than 1W.