PERFORMANCE ISSUES IN INTEGRATING TEMPORALITY-BASED CACHING WITH PREFETCHING

This work evaluates the performance effectiveness of combining two tec hniques for improving cache hit rate and reducing memory traffic in sm all on-chip direct-mapped caches. Temporality-based caching is an effi cient technique for reducing unnecessary cache block conflicts in dire ct-mapped caches, but does not address compulsory misses. Tagged prefe tching is a known technique for controlling compulsory misses, but has the potential for introducing high block interference, cache pollutio n and increased memory traffic in small direct-mapped caches. We propo se and evaluate a group of caching strategies that integrate various c ombinations of temporality-based caching and tagged prefetching. Some combinations show both a remarkable improvement in hit rate and a subs tantial reduction in memory traffic.