VHDL SYNTHESIS DESCRIPTION PORTABILITY - THE NEED FOR LEVEL SYNTHESISSUBSETS

Synthesis represents today one of the most important applications of V HDL with a high user demand. Nevertheless, VHDL lacks a standard synth esis methodology and, as a consequence, each synthesis tool imposes it s own synthesis methodology on the user. This fact has many disadvanta ges; the main one is the lack of portability. In this paper, the activ ities of the European VHDL Synthesis Working Group towards the definit ion of a Level-0 synthesis subset will be described. The Level-0 subse t will constitute a standard subset of VHDL for synthesis applications which will allow description portability between tools as well as des ign reusability, Their contents will be described and their advantages and limitations commented on.