BANDWIDTH OF A RECONFIGURABLE MULTIPLE-GROUP MULTIPROCESSOR SYSTEM

This paper discusses the multiprocessor model using multiple bus as th e interconnection network is presented, In this model N processors, B buses, and M memory modules are connected in groups. The collapse of o ne or more of those memory modules, processors, and buses can lead to the loss in the performance of the whole system, if not collapsed comp letely. A graceful degradable scheme for the reconfiguration of proces sors is also presented. Thus the system becomes a multiple-group multi ple-bus system. The bandwidth of every multiple-bus system is calculat ed and summed together for the calculation of the entire system bandwi dth.