PARALLEL ARCHITECTURE OF ADAPTIVE MTD PROCESSORS

Authors
KABAKCHIEV C BEHAR V
Citation
C. Kabakchiev et V. Behar, PARALLEL ARCHITECTURE OF ADAPTIVE MTD PROCESSORS, Mathematics and computers in simulation, 42(1), 1996, pp. 97-105
Citations number
6
Categorie Soggetti
Computer Sciences",Mathematics,"Computer Science Interdisciplinary Applications","Computer Science Software Graphycs Programming
Journal title
Mathematics and computers in simulation → ACNP
ISSN journal
03784754
Volume
42
Issue
1
Year of publication
1996
Pages
97 - 105
Database
ISI
SICI code
0378-4754(1996)42:1<97:PAOAMP>2.0.ZU;2-O
Abstract
A parallel systolic structure of the adaptive moving target detector ( AMTD) is described. The adaptive signal processing is realized in the whole area of observation by a set of systolic processors operating in parallel. The cost of systolic AMTD implementation (necessary number of processing elements and computational steps) is also evaluated.