GATE ETCH INDUCED DIODE LEAKAGE PREVENTION WITH 7-NM CVD STACKED GATEDIELECTRIC

Using a CVD stacked oxide, containing a thermally grown layer and a de posited CVD film, as the gate dielectric for MOS devices provides sign ificant advantages over a single thermally grown oxide, due to mismatc h of weak spots in the two layers, reduced substrate consumption and s tress compensation between component layers, This paper discusses how a 7-nm stacked gate oxide reduced process-induced diode leakage by sim ilar to 10(2), an advantage not reported previously, Micropore misalig nment in the two component layers of the stacked gate oxide preventing the reactive etchant ions from reaching the substrate could explain t he enhanced ''etch stop'' provided by the stacked oxide.