We present experimental results of superconducting voltage-state compl
ementary output switching logic gates operating 10 Gb/s and 2-bit enco
der circuits clocked at 5-8 Gb/s. The logic gates and circuits were de
signed using a Monte Carlo optimization process so that they have a hi
gh theoretical yield at 5-10 Gb/s in spite of existing Josephson junct
ion process variations. (C) 1996 American Institute of Physics.