TECHNOLOGY MAPPING FOR FPGAS WITH COMPOSITE LOGIC BLOCK ARCHITECTURES

A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs o f different sizes and AT&T ORCA is another example containing both LUT s and logic gates. We use a multiple-fanout pattern graph library to m odel the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new cove ring algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technolog y mapper for FPGAs with composite logic block architectures, especiall y for large circuits. Over a set of MCNC benchmarks, our algorithm req uires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TE MPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Ov er a set of larger benchmarks, our algorithm outperforms PPR by 13.70% . Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.