ANALYSIS AND PREVENTION OF DRAM LATCH-UP DURING POWER-ON

The occasional power-on latch-up phenomenon of DRAM modules with a dat a bus shared by multiple DRAM chips on different modules was investiga ted and the circuit techniques for latch-up prevention were presented, Through HSPICE simulations and measurements, the latch-up triggering source was identified to be the excessive voltage drop at the n-well p ick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which hows when the bus contention occurs d uring power-on, By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I -V and C-V data, HSPICE simulations were performed for the power-on la tch-up phenomenon of DRAM chips, Good agreements were achieved between measured and simulated voltage waveforms, In order to prevent the pow er-on latch-up even when the control signals (RAS, GAS) do not track w ith the power supply, two circuit techniques were presented to solve t he problem, One is to replace the CMOS transmission gate by a CMOS tri state inverter in the DRAM chip design and the other is to start the C AS-BEFORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period.