A 200 MHZ REGISTER-BASED WAVE-PIPELINED 64M SYNCHRONOUS DRAM

A new register-based wave-pipelined scheme for synchronous DRAM's (SDR AM's) is proposed. In this scheme, (N-1) registers are located between a read data bus line pair and a data output buffer and (N-1) read dat a are stored in parallel in these registers, where N denotes the CAS l atency. Since the column data path is not divided and the read data is transmitted directly to the registers, the burst read operation can e asily be achieved at a higher operation frequency without a large area penalty of degradation of an internal timing margin, Measured results show that the 64M SDRAM based on the register-based wave-pipelined sc heme can operate up to 200 MHz.