A PIPELINED MULTIPLIER-ACCUMULATOR USING A HIGH-SPEED, LOW-POWER STATIC AND DYNAMIC FULL ADDER DESIGN

This paper proposes a new pipelined full-adder circuit structure for t he implementation of pipelined arithmetic modules. With both static an d dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio, The adder c ell is then used to design a pipelined 8 x 8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduc e the latency, The MAC is fabricated in a 0.8-mu m single-poly-double- metal CMOS process, The post-layout simulation shows that the pipeline d 1-b full adder can work up to 350 MHz with a 3 V power supply, The w hole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply.