A CURRENT-MODE BIT-BLOCK CIRCUIT APPLICABLE TO LOW-VOLTAGE, LOW-POWERPIPELINE VIDEO-SPEED A D CONVERTERS/

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed a nalog-and-digital MOS LSIs. To examine this, we designed and circuit s imulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approa ch. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Cu rrent mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the desi gn. Operation with a 3 V power supply and a 20 MHz clock speed in a 3- bit A/D configuration was verified through circuit simulation using st andard CMOS 0.6 mu m device parameters. Gain error, mismatch of curren t, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2 % (10-bit level), a linearity error of less than 0.1% (more than 10-bi t level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realize d without calibration. This confirms that the current-mode approach is effective.