AREA-TIME-POWER TRADEOFFS IN PARALLEL ADDERS

In this paper, several classes of parallel, synchronous adders are sur veyed based on their power, delay and area characteristics. The adders studied include the linear time ripple carry and manchester carry cha in adders, the square-root time carry skip and carry select adders, th e logarithmic time carry lookahead adder and its variations, and the c onstant time signed-digit and carry-save adders, Most of the research in the last few decades has concentrated on reducing the delay of addi tion, With the rising popularity of portable computers, however, the e mphasis is on both high speed and low power operation. In this paper w e adopt a uniform static CMOS layout methodology whereby short circuit power minimization is used as the optimization criterion, The relativ e merits of the different adders are evaluated by performing a detaile d transistor-level simulation of the adders using HSPICE, Among the tw o's complement adders, a variation of the carry lookahead adder, calle d ELM, was found to have the best power-delay product, Based on the re sults of our experiments, a large adder design space is formulated fro m which an architect can choose an adder with the desired characterist ics.