The paper describes a new 50 V BiCMOS smart power process. The develop
ment includes the monolithic integration of dielectrical isolated 1.5
mu m CMOS devices, NPN/PNP bipolar transistors, 50 V vertical and quas
ivertical DMOS power transistors, poly-n(+) capacitors, Zener diodes,
implanted resistors and double metal wiring. The process will be used
to fabricate efficient and self protected circuits with integrated dio
de or DMOS full bridges.