ON THE OPTIMIZATION OF OUTSIDE SPACER BIPOLAR-TRANSISTORS FOR 0.5-MU-M HIGH-PERFORMANCE MIXED ANALOG DIGITAL BICMOS/

For high performance mixed analog/digital and ECL-CMOS applications th e inside spacer, double poly bipolar structure has attracted most atte ntion. Although this structure offers superior performance over it's o utside spacer counterpart, a significant increase in the cost and comp lexity of the BiCMOS process is incurred especially when combined with trench isolation and composite material inside spacers. In this paper we examine different approaches for enhancing the performance of CMOS compatible outside spacer transistors opening up the possibility for lower complexity, high performance BiCMOS processes. As a vehicle for this work we report on the integration of outside spacer bipolar trans istors in a baseline digital 0.5 mu m, 3.3 Volt, triple level metal CM OS technology. Transistors with peak f(T) (extracted as gain bandwidth ) of 17-18 GHz, BVceo greater than or equal to 5 Volts and Early volta ge V-A of 25-30 Volts are reported. Future lateral and vertical scalin g is expected to yield performance which compares favourably to more c omplex inside spacer processes.