INCORPORATING PERFORMANCE AND TESTABILITY CONSTRAINTS DURING BINDING IN HIGH-LEVEL SYNTHESIS

Module and register binding during high-level synthesis is one of the most important steps in generating an RTL design from a behavioral des cription, The binding phase determines the structure of the final desi gn, and hence issues related to area, performance and testability of t he RTL design have to be addressed in this step. In this paper, we pre sent algorithms for module and register binding which generate RTL des igns having high performance and/or high testability, The binding prob lem is decomposed into a sequence of subproblems, each of which is mod eled as a minimum-cost network flow problem. The relative impact of th e possible bindings Is expressed in terms of the costs associated with the edges of the network. The model is simple and can be solved quick ly to obtain a low cost flow solution, Putting together the solutions to the subproblems gives low cost bindings. We also propose cost funct ions that can be used with varying emphasis on delay and testing, The results demonstrate the effectiveness of our algorithm; the final desi gns produced by the algorithms require a smaller clock cycle or are ea sier to test as compared to designs generated without the performance or testability constraints.