TECHNOLOGY MAPPING FOR TLU FPGAS BASED ON DECOMPOSITION OF BINARY DECISION DIAGRAMS

This paper proposes an efficient algorithm for technology mapping targ eting table look-up (TLU) blocks, It is capable of minimizing either t he number of TLU's used or the depth of the produced circuit. Our appr oach consists of two steps, First a network of super nodes, is created , Next a Boolean function of each super node with an appropriate don't care set is decomposed into a network of TLU's, To minimize the circu it's depth, several rules are applied on the critical portion of the m apped circuit.