DEFECT LEVEL EVALUATION IN AN IC DESIGN ENVIRONMENT

The purpose of this paper is to present a methodology for the evaluati on of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to nonequiprobable f aults, which are collected from the IC layout, using the information o n a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models, It is shown that DL depends on the critical areas associated with undetected faults, an d their correspondent defect densities, Simulation results are present ed, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality, Moreover, results sho w that the efficiency of a given set of test patterns strongly depends on the physical design and defect statistics.