A 0.3-mu m 4-Mb BICMOS SRAM with a 6-ns access time at a minimum suppl
y voltage of 1.5 V has been developed, Circuit technologies contributi
ng to the low-voltage, high-speed operations include: 1) boost-BiNMOS
gates for address decoding circuits; 2) an optimized word-boost techni
que for a highly-resistive-load memory cell; 3) a stepped-down CML cas
coded bipolar sense amplifier; 4) optimum boost-voltage detection circ
uits with dummies for boost-voltage generators.