A 1-V, 100-MHZ, 10-MW CACHE USING A SEPARATED BIT-LINE MEMORY-HIERARCHY ARCHITECTURE AND DOMINO TAG COMPARATORS

A l-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricat ed using a 0.25-mu m CMOS technology for future low-power high-speed m icroprocessors. Effective latency of 6.9 ns and power consumption of 1 0 mW at 100 MHz are obtained at a supply voltage of 1 V, This performa nce is achieved by using a new separated bit-line memory hierarchy arc hitecture (SBMHA) that speeds up latency and reduces power consumption , and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons.