A 60-NS 1-MB NONVOLATILE FERROELECTRIC MEMORY WITH A NONDRIVEN CELL PLATE LINE WRITE READ SCHEME/

This paper proposes three circuit technologies for achieving mega-bit- class nonvolatile ferroelectric RAM's (NVFRAM's), The proposed nondriv en cell plate line write/read scheme (NDP scheme) accomplishes fast wr ite/read operation equivalent to that of DRAM's, Problems and counterm easures in introducing this scheme into NVFRAM's are also discussed, A proposed optimized C-B/C-S cell array design method provides a relati onship between bit line capacitance C-B and memory cell capacitance C- S, which must be satisfied for read operations, Also reported is a ref erence voltage generator circuit that uses a dummy memory cell, This c ircuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM, A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-mu m CMOS process, This chip has an acces s time of 60 ns and a die size of 15.7 x 5.79 mm(2).