A 1.6-GB S DATA-RATE 1-GB SYNCHRONOUS DRAM WITH HIERARCHICAL SQUARE-SHAPED MEMORY BLOCK AND DISTRIBUTED BANK ARCHITECTURE/

This paper describes key techniques for a 1.6-GB/s high data-rate l-Gb synchronous DRAM (SDRAM), Its high data transfer rate and large memor y capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-d imensional (3-D) graphics frame memory in a time sharing fashion, The 200-MHz high-speed operation is achieved by the unique hierarchical sq uare-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 mu m(2) cell and 581.8 mm(2) small die a rea are achieved using 0.15-mu m CMOS technology, The x64 chip uses 19 6-pin EGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also describ ed.