A 2.5-NS CLOCK ACCESS, 250-MHZ, 256-MB SDRAM WITH SYNCHRONOUS MIRROR DELAY

Authors
SAEKI T NAKAOKA Y FUJITA M TANAKA A NAGATA K SAKAKIBARA K MATANO T HOSHINO Y MIYANO K ISA S NAKAZAWA S KAKEHASHI E DRYNAN JM KOMURO M FUKASE T IWASAKI H TAKENAKA M SEKINE J IGETA M NAKANISHI N ITANI T YOSHIDA K YOSHINO H HASHIMOTO S YOSHII T ICHINOSE M IMURA T UZIIE M KIKUCHI S KOYAMA K FUKUZO Y OKUDA T
Citation
T. Saeki et al., A 2.5-NS CLOCK ACCESS, 250-MHZ, 256-MB SDRAM WITH SYNCHRONOUS MIRROR DELAY, IEEE journal of solid-state circuits, 31(11), 1996, pp. 1656-1668
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
31
Issue
11
Year of publication
1996
Pages
1656 - 1668
Database
ISI
SICI code
0018-9200(1996)31:11<1656:A2CA22>2.0.ZU;2-T
Abstract
A 256-Mb SDRAM (245.7 mm(2)) has been developed using 1) a high cell o ccupation ratio (60.2%) array design for chip size reduction and a hig h yield, 2) a prefetched pipeline scheme (PPS) using a first-in first- out (FIFO) buffer with parallel serial converter for 250-MHz clock fre quency operation, and 3) a synchronous mirror delay (SMD) circuit for 2,5-ns clock access and low standby current.