A 0.9-V, 150-MHZ, 10-MW, 4 MM(2), 2-D DISCRETE COSINE TRANSFORM CORE PROCESSOR WITH VARIABLE THRESHOLD-VOLTAGE (VT) SCHEME

Authors
KURODA T FUJITA T MITA S NAGAMATSU T YOSHIOKA S SUZUKI K SANO F NORISHIMA M MUROTA M KAKO M KINUGAWA M KAKUMU M SAKURAI T
Citation
T. Kuroda et al., A 0.9-V, 150-MHZ, 10-MW, 4 MM(2), 2-D DISCRETE COSINE TRANSFORM CORE PROCESSOR WITH VARIABLE THRESHOLD-VOLTAGE (VT) SCHEME, IEEE journal of solid-state circuits, 31(11), 1996, pp. 1770-1779
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
31
Issue
11
Year of publication
1996
Pages
1770 - 1779
Database
ISI
SICI code
0018-9200(1996)31:11<1770:A0114M>2.0.ZU;2-A
Abstract
A 4 mm(2), two-dimensional (2 D) 8 x 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-mu m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissip ation of a previous 3.3-V design. Circuit techniques for dynamically v arying threshold voltage (VT scheme) are introduced to reduce active p ower dissipation with negligible overhead in speed, standby power diss ipation, and chip area. A way to explore V-DD - V-th design space is a lso studied.