A CMOS 6-B, 200 MSAMPLE S, 3 V-SUPPLY A/D CONVERTER FOR A PRML READ CHANNEL LSI/

A CMOS 6-b, 200 MSample/s, (MS/s) flash A/D converter (ADC) with 3 V p ower supply has been developed for a mixed-signal partial-response max imum likelihood (PRML) read channel LSI, In a CMOS flash ADC with chop per comparators, all comparators are auto-zeroed prior to each convers ion, As a result, half of the available comparison time is spent auto- zeroing, To improve conversion rate and performance when included in a mixed-signal LSI, the auto-zeroing rate was reduced using a newly dev eloped ''interleaved auto-zeroing'' (IAZ) architecture. Less frequent auto-zeroing also reduces kickback noise to the analog input and refer ence resistor string and power supply noise. In addition, the comparat or output-swing is limited to improve recovery from large overdrives b y adding diode connected transistors, This ''output-swing limiting com parator'' (OLC) improved the response to high frequency analog inputs, A conversion rate of 200 MS/s was achieved in the PRML read channel L SI using the IAZ architecture and OLC,This ADC was fabricated with sin gle poly-Si, double-Metal, 0.5-mu m CMOS technology.