AN INTERCONNECT ALLOCATION ALGORITHM FOR PERFORMANCE-DRIVEN DATAPATH SYNTHESIS

This paper presents the design of a performance-driven interconnect al location algorithm. The proposed algorithm is based on the idea that t he data transfer time can be reduced by balancing the load for specifi c hardware modules on possible critical path, such that the clock peri od can be minimized. By performing load balancing for only the communi cation lines on critical paths, the proposed algorithm generates inter connection structures with minimum delays. Experimental results confir m the effectiveness of the algorithm by constructing the interconnecti on structures with minimized clock periods for several benchmark circu its available from the literature.