EFFICIENT SYNTHESIS ALGORITHM FOR LOW-POWER ASIC DESIGN

Authors
LEE HD LEE JS HYUN MH HWANG SY
Citation
Hd. Lee et al., EFFICIENT SYNTHESIS ALGORITHM FOR LOW-POWER ASIC DESIGN, Electronics Letters, 32(22), 1996, pp. 2060-2062
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
32
Issue
22
Year of publication
1996
Pages
2060 - 2062
Database
ISI
SICI code
0013-5194(1996)32:22<2060:ESAFLA>2.0.ZU;2-0
Abstract
The authors propose an efficient synthesis algorithm for the synthesis of RT-level hardware with low power consumption. The proposed algorit hm minimises the overall power consumption of generated datapath by re ducing spurious operations. Experimental results for several benchmark circuits under various synthesis constraints show the efficiency of t he proposed algorithm.