LOW-POWERED 2.1-MU-S BINARY DELAY-LINE IN RADIATION-HARD SOI-BICMOS TECHNOLOGY

The requirements of the presented binary delay line are low power, sma ll area and minimum delay of 2 mu s at a clock rate of 40MHz. This bin ary delay line is implemented in 0.8 mu m radiation hard SOI-SIMOX BiC MOS-PJFET technology of DMILL and consumes <450 mu W/channel for a des ign with four channels and is part of a larger read-out chip for capac itive detectors.