Ss. Nayak et Pk. Meher, 3-DIMENSIONAL SYSTOLIC ARCHITECTURE FOR PARALLEL VLSI IMPLEMENTATION OF THE DISCRETE COSINE TRANSFORM, IEE proceedings. Circuits, devices and systems, 143(5), 1996, pp. 255-258
Two different linear systolic arrays have been suggested for the compu
tation of discrete cosine transform (DCT). The proposed linear arrays
are complementary to each other in the sense that the output of the li
near arrays of one type may be fed as the input for the linear arrays
of the other type. This feature of the proposed linear arrays has been
utilised for designing a bilayer structure for computing the prime-fa
ctor DCT. It is interesting to note that the proposed structure does n
ot require any hardware/time for transposition of the intermediate res
ults. The desired transposition is achieved by orthogonal alignment of
the linear arrays of the upper layer with respect to those of the low
er layer. The proposed structures provide high throughput of computati
on due to fully pipelined processing, and massive parallelism employed
in the bilayer architecture.