HARDWARE REDUCTION IN CONTINUOUS CHECKSUM-BASED ANALOG CHECKERS - ALGORITHM AND ITS ANALYSIS

Fault-tolerant design of analog circuits is more difficult than that o f digital circuits. Chatterjee has proposed a continuous checksum-base d technique to design fault-tolerant linear analog circuits. However, hardware overhead of the embedded checker is an important issue in thi s technique, which has never been addressed before. This paper propose s an algorithm for reduction of hardware overhead in the checker. With out changing the original circuit, the proposed algorithm can not only reduce the number of passive elements, but also the number of analog operators so that the error detection circuitry in the checker has opt imal hardware overhead. As the basis of the algorithm, a serial of the oretic results, including the concept and existence conditions of all- non-zero solutions, have also been presented to verify the algorithm.