DESIGN METHOD FOR A DIGITALLY TRIMMABLE MOS-TRANSISTOR STRUCTURE

A digitally trimmable MOS transistor is a MOS transistor consisting of a drain, a source, and a main gate, as well as several subgates. The transconductance of the transistor is digitally tunable by means of co nnecting subgates either to the main gate or to the source terminal. I n the paper a systematic design method for a digitally trimmable MOS t ransistor structure is proposed. Using the proposed method, we have de signed a digitally trimmable MOS transistor structure, and fabricated prototype devices in a 2.4 mu m n-well CMOS technology. Through measur ement on these devices, the design method has been experimentally conf irmed. The trimmable MOS transistor structure has been applied to a hi gh precision current mirror to reduce mismatch in the current mirror. With the trimmable transistor structure, the mismatch can be reduced b y more than one order of magnitude.