A HYBRID-SEED SMART PIXEL ARRAY FOR A 4-STAGE INTELLIGENT OPTICAL BACKPLANE DEMONSTRATOR

This paper describes the VLSI design, layout, and testing of a Hybrid- SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGa As multiple-quantum-well modulators and detectors. The chip has been d esigned based on the HyperPlane architecture and is composed of four s mart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accom modate for optical inversions and bit permutations by appropriate sele ctions of multiplexers. Initial data pertaining to the electrical perf ormance of the chip will be provided and a complete logical descriptio n will be given.