We describe Our work on the design and testing of optical receivers fo
r use in optoelectronic VLSI, Tile focal nature of the optoelectronic
VLSI system permits novel receiver designs, incorporating multiple opt
ical beams and/or synchronous operation, while the requirement of real
izing large numbers of cr a receivers on a single chip severely constr
ains al ea and power consumption. We describe four different receiver
designs, and their different operating modes. Results include 1-Gb/s h
igh-impedance, two-beam diode-clamped PET-SEED receivers, single and d
ual-beam transimpedance receivers realized with a hybrid attachment of
multiple-quantum well devices to 0.8-mu m linewidth CMOS operating to
1 Gb/s, and synchronous sense-amplifier-based optical receivers with
low (similar to 1 mW) power consumption. Finally, we introduce a measu
re of receiver performance that includes area and power consumption.