A MODEL STUDY OF THERMAL STRESS-INDUCED VOIDING IN ELECTRONIC PACKAGES

Thin film metallizations are one of the most important interconnects i n large-scale integrated circuits. They are covered by substrates and passivation films. Large hydrostatic (mean) tension develops due to th e constraint and thermal mismatch, and voiding is identified as the fa ilure mechanism. This phenomenon of rapid nucleation and growth of voi ds is called cavitation instability and it can lead to the failure of ductile components in electronic packages such as metallizations. A mi cromechanics model is developed to provide the critical mean stress le vel that will trigger the cavitation instability. It is found that thi s critical mean stress level, the cavitation stress, not only depends on the material properties but also is very sensitive to defects in th e material. For example, the cavitation stress decreases drastically a s the void volume fraction increases. The stress-based design criterio n for ductile components in electronic packages should then be: (1) Va n Mises effective stress < yield stress; and (2) mean stress < cavitat ion stress, which is particularly important to the constrained ductile components in electronic packages such as vias and conductive adhesiv es. An analytical expression of cavitation stress for elastic-perfectl y plastic solids is obtained, and numerical results for elastic-power law hardening solids are presented.