ANALYSIS, ESTIMATION AND REDUCTION OF SIM ULTANEOUS SWITCHING NOISE

The performance of digital and mixed circuits is affected and limited by the simultaneous switching power and ground noise. This kind of noi se is related to interconnections and packaging. The latter two factor s play a major role in high-speed-circuit design and may become a domi nant factor limiting the performance of future ULSI components. As a r esult, it is imperative to understand and to master the problems and s ubtleties arising from interconnections and packaging. Among these pro blems, that of simultaneous switching noise is taking on more and more importance as circuits become faster and their I/O pin count increase s. This paper reviews the state of current research regarding how to a nalyze, estimate and reduce simultaneous switching noise.