FAST AND GATE-COUNT EFFICIENT ARITHMETIC-LOGIC UNIT

Authors
LEE YS JOH P YOU JH PARK KT
Citation
Ys. Lee et al., FAST AND GATE-COUNT EFFICIENT ARITHMETIC-LOGIC UNIT, Electronics Letters, 32(23), 1996, pp. 2126-2127
Citations number
3
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
32
Issue
23
Year of publication
1996
Pages
2126 - 2127
Database
ISI
SICI code
0013-5194(1996)32:23<2126:FAGEAU>2.0.ZU;2-3
Abstract
CMOS arithmetic logic unit is presented with a minimum number of trans istors and high speed arithmetic operations. Multiple carry chain adde rs, a novel 1 bit adder, are used in a carry select adder. The carry c hain adder has a high degree of shared gates with a low propagation de lay.