FAILURE ANALYSIS AND NEW DESIGN OF A THIN-FILM SILICON-ON-INSULATOR POWER METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR BASED ON EMISSION MICROSCOPY AND 2-DIMENSIONAL DEVICE SIMULATION

Thin-film silicon-on-insulator (SOI) power metal-oxide-semiconductor f ield-effect transistors (MOSFETs) with a standard stripe-gate topology and a cellular-gate topology have been fabricated. The breakdown volt age for the stripe-gate topology is half that for the cellular-gate to pology in 200-V-class power MOSFETs. Their failure modes are analyzed by emission microscopy and 2-dimensional device simulation for the fir st time and a new device structure is proposed based on the results of this analysis. The fabricated new device attains a breakdown voltage of 200 V and a specific on-resistance of 2.7 Omega . mm(2).