A MODEL FOR THRESHOLD VOLTAGE SHIFT UNDER POSITIVE AND NEGATIVE-HIGH-FIELD ELECTRON INJECTION IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) TRANSISTORS

High-field electron injection is an attractive tool for investigation of properties of thin dielectric layers. The paper discusses the thres hold voltage degradation of complementary metal-oxide-semiconductor (C MOS) devices due to high field oxide stressing. Both the filling of ex isting oxide hole and electron traps and the generation of new defects , namely bulk electron traps and interface states, are carefully consi dered. It is shown that monitoring of stress voltage transients during constant-current electron injection into the device gate oxide may be very helpful in understanding degradation phenomena. A qualitative mo del is proposed to explain different behavior and susceptibility of th e threshold voltage of CMOS devices to F-N stress-induced degradation. The model is based on differences in charge trapping and detrapping i n different regions of very thin gate oxides under different stress co nditions in p-type MOS (PMOS) and n-type MOS (NMOS) transistors.