EFFICIENT APPROACHES TO TESTING VHDL DSP MODELS

Generation of test benches for large DSP behavioral models is a compli cated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the m odeler of the details of this task. High level design tools are used t o develop the test bench VHDL code. The test bench code models sensors which drive the Model Under Test (MUT), Data files which can also dri ve the MUT are prepared by environmental data generators. The system s pecification values are linked to the testbench via requirements captu re tools and test plans. Intelligent interfaces are used to control th e development and simulation of the test bench. The approach is applic able to the testing of any DSP system modeled in the VHDL language. It provides the modeler with the capability to rapidly test DSP models a nd adjust the model test environment to frequent changes in system req uirements.