ARCHITECTURE AND APPLICATIONS OF THE HIPAR VIDEO SIGNAL PROCESSOR

In this paper, we propose the architecture of a highly parallel DSP (H iPAR-DSP) as a flexible and programmable processor for image and video processing. The design of this processor is based on an analysis of c haracteristic properties of image processing algorithms in terms of av ailable parallelization resources, demands on program control, and req uired data access mechanisms. This led to a very long instruction word (VLIW)-controlled ASIMD RISC-architecture with four or sixteen data p aths, employing data-level parallelism, parallel instructions, micro-i nstruction pipelining, and data transfer concurrently to data processi ng. Common data access patterns for image processing algorithms are su pported by use of a shared on-chip memory with parallel matrix type ac cess patterns and a separate data-cache per data path, By properly bal ancing processing and controlling capabilities as internal and externa l memory bandwidth, this approach is optimized to make best use of cur rently available silicon resources. A high clock frequency is achieved by implementation of classic RISC features. The architecture fully su pports high level language programming. With the 16 data path version at 100 MHz clock, a sustained performance of more than 2 billion arith metic operations per second (GOPS) is achieved for a wide range of alg orithms. Given examples show the parallel implementation of image proc essing algorithms like histogramming, Hough transform, or search in a sorted list with efficient use of the processor resources. A prototype of the architecture with four parallel data paths will be available i n the second quarter of 1996, using a 0.6 mu m CMOS technology.